The present invention relates to clock circuitry and, more particularly, to methods and circuits that generate clock signals indicating when to read and write data on a bus.
Clock signals are used in electrical circuits to control the flow of data on data communication busses and control the timing and processing of various functions. In particular systems, data is written to a data bus or read from the data bus based on the state of one or more clock signals. These clock signals are necessary to prevent xe2x80x9ccollisionxe2x80x9d of data, i.e., the simultaneous transmission of data by two different devices on the same data bus. The clock signals also ensure that the desired data is available on the data bus when read by a device.
FIG. 1 illustrates a particular example of a data storage system 100. A memory controller 102 controls the writing and reading of data to and from one or more memory storage modules 104, 106, and 108. Memory storage modules 104, 106, and 108 may contain any number of memory storage devices, such as random access memories (RAMs). The memory controller 102 and memory storage modules 104-108 are coupled to a data bus 110 and a clock signal transmitted on a pair of lines 112a and 112b. The clock signal may be single-ended or differential. The data bus 110 communicates data between the memory storage modules 104-108 and the memory controller 102. Lines 112a and 112b transmit a clock signal generated by a clock generator 120, coupled to line 112a. Line 112a is xe2x80x9clooped backxe2x80x9d to line 112b as it passes through memory controller 102. The clock signal carried by line 112a may be referred to as CTM (clock to master or clock to memory controller) and the clock signal carried by line 112b may be referred to as CFM (clock from master or clock from memory controller). Line 112b and each of the lines in data bus 110 are terminated through a resistor 114, which is coupled to Vcc.
FIG. 2 is a timing diagram illustrating the process for reading data from a data bus and writing data to a data bus, such as data bus 110 discussed above with respect to FIG. 1. The signal xe2x80x9cBUS CLKxe2x80x9d is the bus clock signal that sets the timing for data read and write operations on the data bus. In this example, BUS CLK is a square wave signal having a 50% duty cycle. Both edges of BUS CLK are centered on the corresponding data. Data is transmitted on the data bus corresponding to the rising edge of BUS CLK (referred to as xe2x80x9codd dataxe2x80x9d) and corresponding to the falling edge of BUS CLK (referred to as xe2x80x9ceven dataxe2x80x9d). Thus, data is transmitted twice during each cycle of BUS CLK plus an output driver delay (Tod). A signal T-CLK, which identifies when data is transmitted on the data bus, is 90 degrees ahead of BUS CLK. Another signal R-CLK, which identifies when data is read from the data bus, is aligned with BUS CLK. A DATA signal indicates when data is available on the data bus.
As shown in FIG. 2, the R-CLK signal is adjusted to account for the setup time (Tsu) necessary to communicate the appropriate data to the data bus. To ensure that the edge of BUS CLK aligns with the center of the available data, the 90 degree center point of the data on the data bus must be Tsu seconds before the corresponding sampling edge of the internal R-CLK.
FIG. 3 illustrates a circuit 150 capable of generating the T-CLK and R-CLK signals shown in FIG. 2. Circuit 150 is contained in a memory controller, such as the memory controller shown in FIG. 1. The circuit 150 includes a first delay-locked loop to generate R-CLK and includes a second delay-locked loop to generate T-CLK. A clock amplifier 152 receives the BUS CLK signal, amplifies the BUS CLK signal, and provides a differential signal having a 50% duty cycle and the desirable common mode to a reference loop 154. Reference loop 154 creates a quadrature wave form and provides that signal to a pair of fine loop circuits 156 and 166. Each fine loop circuit 156 and 166 forms part of a delay-locked loop. Fine loop circuit 156, in combination with a clock buffer 158 and a phase detector 164 form a first delay-locked loop, which generates the R-CLK signal. Phase detector 164 identifies the current phase of the R-CLK signal and provides an adjustment signal to fine loop circuit 156. This adjustment is necessary to account for the setup time (Tsu) necessary to communicate the appropriate data to the data bus. The delay-locked loop created by fine loop 156, clock buffer 158 and phase detector 164 ensures that the proper setup time Tsu is taken into account when generating the R-CLK signal. Thus, a receiver 160 will retrieve data from a bus 162 at the appropriate time (i.e., at the center of the valid data).
Fine loop circuit 166, in combination with a clock buffer 168, a delay device 172, and a quadrature phase detector 174 form a second delay-locked loop, which generates the T-CLK signal. Quadrature phase detector 174 creates the necessary 90 degree shift of the T-CLK signal from the BUS CLK signal (see FIG. 2) by providing the appropriate adjustment signal to fine loop circuit 166. Additionally, the adjustment signal provided by delay device 172 is necessary to account for the output driver delay (Tod), discussed above. The delay-locked loop created by fine loop 166, clock buffer 168, delay device 172, and quadrature phase detector 174 creates the necessary alignment of data with the T-CLK signal. Thus, an output driver 170 will drive data onto the bus 162 at the appropriate time.
The circuit described above with respect to FIG. 3 requires two separate delay-locked loops to generate the R-CLK and the T-CLK signals. The use of two delay-locked loops requires a significant amount of power and uses a significant amount of layout area within the memory controller.
An improved architecture described herein addresses these and other problems by simplifying the circuit that generates the R-CLK and the T-CLK signals.
The improved architecture discussed below generates the R-CLK and T-CLK signals using a single delay-locked loop. The use of a single delay-locked loop requires fewer components and reduces the power consumption of the circuit as compared to the circuit described above in FIG. 3. Additionally, the improved architecture requires less area within the memory controller.
In one embodiment, a delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay clement is coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period.
In another embodiment, the delay-locked loop circuit further includes a phase detector to identify phase differences between the first clock signal and the reference clock signal.
In one embodiment, the phase detector is an integration sampler to integrate the first clock signal against the reference clock signal.
In a described implementation, the delay-locked loop circuit includes a 180 degree phase shifter to adjust the phase of the first clock signal.
In a particular embodiment, a third delay element is coupled between the delay-locked loop circuit and the second delay element.